ISA System Arquitecture / Tom Shanley and Don Anderson

Foreword – Acknowledgements – About This book – Overview – Part 1: the System Kernel – Chapter 1: Intro to Microprocessor Communications – Chapter 2: Introduction to the bus Cycle – Chapter 3: Addressing I/O and Memory – Chapter 4: The Address Decode Logic – Chapter 5: The 80286 Microprocessor – Chapter 6: The Reset Logic – Chapter 7: The Power-Up Sequence – Chapter 8: The 80286 System Kernel: The Engine – Chapter 9: Detailed View of the 80286 Bus Cycle – Chapter 10: The 80386 DX and SX Microprocessors – Chapter 11: The 80386 System Kernel – Chapter 12: Detailed View of the 80386 Bus Cycles – Part2: Memory Subsystems – Chapter 13: RAM Memory: Theory of Operation – Chapter 14: Cache Memory concepts – Chapter 15: ROM Memory – Part 3: The Industry Standard Architecture – Chapter 16: ISA Bus Structure – Chapter 17: Types of ISA Bus Cycles – Chapter 18: The Interrupt Subsystem – Chapter 19: Direct Memory Access – Chapter 20: ISA Bus Masters – Chapter 21: ISA Bus Masters – Chapter 21: RTC and Configuration RAM – Chapter 22: Keyboard/mouse Interface – Chapter 23: - Numeric Coprocessor – Chapter 24: ISA Timers – Appendices – I/O Address Map – Glossary of terms - Index

ISA System Architecture describes the hardware architecture of ISA (Industry Standard Architecture) providing a clear, concise explanation of an ISA system in detail / La arquitectura del sistema ISA describe la arquitectura de hardware de ISA (Arquitectura estándar de la industria) proporcionando una explicación clara y concisa de un sistema ISA en detalle.